Method of producing a layered arrangement and layered arrangement

ABSTRACT

An arrangement and process for producing a circuit arrangement is disclosed. The process includes having a layer arrangement, in which two electrically conductive interconnects running substantially parallel to one another are formed on a substrate. At least one auxiliary structure is formed on the substrate and between the two interconnects, running in a first direction, which first direction includes an angle of between 45 degrees and 90 degrees with a connecting axis of the interconnects, running orthogonally with respect to the two interconnects, the at least one auxiliary structure being produced from a material which allows the at least one auxiliary structure to be selectively removed from a dielectric layer. The dielectric layer is formed between the two interconnects, in such a manner that the at least one auxiliary structure is at least partially covered by the dielectric layer.

CROSS REFERENCE TO RELATED APPLICATIONS

This Utility Patent Application claims the benefit of the filing date ofApplication. No. DE 101 61 312.1. filed Dec. 13, 2001 and InternationalApplication No. PCT/DE02/03998. filed Oct. 23, 2002, both of which areherein incorporated by reference.

FIELD OF THE INVENTION

The invention relates to a process for producing a layer arrangement andto a layer arrangement.

BACKGROUND

Electrically insulating layers are required for many applications insemiconductor technology, in particular when forming integrated circuitsin semiconductor substrates (for example in silicon substrates). Ifinsulation layers are formed in an integrated circuit in whichelectrically conductive regions, in particular electrically conductiveinterconnects, are also included, coupling capacitances may resultbetween adjacent interconnects and a dielectric layer arranged betweenthem. The capacitance C of two parallel interconnects, the mutuallyadjacent surfaces of which are denoted by A and which are arranged at adistance d from one another, is, at a relative dielectric constant ε:C=εA/d  (1)

With ongoing miniaturization in silicon microelectronics, i.e. as thedistance d between adjacent interconnects decreases, a high couplingcapacitance C results in particular if the mutually adjacent surfaces Aof the interconnects are large, i.e. if the interconnects run parallelto one another over a considerable length in the integrated circuit. Bycontrast, the coupling capacitance of two lines which cross one anotheris lower.

Problems with coupling capacitances are intensified by the ongoingminiaturization of integrated circuits. As the coupling capacitanceincreases, the propagation time of a signal in the electrical couplingmeans becomes ever longer, since this propagation time is determined bythe product of resistance R and capacitance C (known as the “RC delay”).

As can be seen from equation (1), with fixed structure dimensions A, d,it is possible to reduce a coupling capacitance if the relativedielectric constant ε of the insulating material is reduced. It istherefore attempted to use materials with a low relative dielectricconstant ε (known as “low-k materials”) as materials for insulationlayers in integrated circuits.

Amorphous silicon dioxide (SiO₂) with a relative dielectric constant ofapproximately 4.0 is often used as dielectric for electricallyinsulating metallic interconnects from one another. It is possible tofurther reduce the dielectric constant of a material for an electricallyinsulating layer if silicon oxide material which additionally containsfluorine, hydrogen or alkyl groups (in particular CH groups) is used forthis purpose. This makes it possible to reduce the relative dielectricconstant to as little as 2.5. Furthermore, organic materials, inparticular polymers, such as for example SiLK™ (a dielectric produced byThe Dow Chemical Company and marketed under the abovementioned tradename) or PBO (polybenzoxazole), are used, making it possible to achieverelative dielectric constants of 2.7. It is also possible for the “low-kmaterials” used to be materials based on silicon, such as for example asilicon-oxygen-fluorine compound, a silicon-carbon-oxygen-hydrogencompound, hydrogen silsesquioxane (HSQ) or methyl silsesquioxane (MSQ).

The relative dielectric constant of electrically insulating layers canbe reduced further by introducing cavities into the “low-k material”.The k value of the porous material is reduced further as a function ofthe proportion of the volume formed by the cavities or pores.

FIG. 1A illustrates a diagram 100 which is known from Steinhögl, W,Schindler, G (2001) “Towards Minimum k Values of Porous Dielectrics: ASimulation Study”, Advanced Metallization Conference, Oct. 9-11, 2001,Montreal. The k value k_(hom) of a homogenous material is plotted on theabscissa 101, and the associated k value k_(por) which is obtained ifpores are introduced into the homogenous material is plotted on theordinate 102. A first curve 103 shows the dependent relationshipdescribed if the cavities form 40% of the volume of the dielectric. Asecond curve 104 shows the dependent relationship described if thecavities form 50% of the volume of the dielectric, and a third curve 105shows the dependent relationship if the cavities form 60% by volume ofthe dielectric. The curves 103 to 105 were obtained from modelcalculations calculated using effective medium approximation, anapproximation method described in Aspnes, DE “Determination of OpticalProperties by Ellipsometry” in “Handbook of Optical Constants ofSolids”, Academic Press, 1985, pp. 104ff. The diagram 100 also shows anumber of data points 106 which were obtained by calculation with thecavities forming 50% by volume, by numerically solving the Maxwellequations using a finite element simulation. It can be seen from FIG. 1Athat the higher the proportion of the volume formed by cavities, thegreater the extent to which the k value k_(por) in a porous material isreduced compared to the k value k_(hom) in a homogenous material. A kvalue of 2.0 can be reached by introducing pores into the dielectric.

However, this method is unable to satisfy the demands imposed by theITRS Roadmap (“International Technology Roadmap for Semiconductors”) onthe k value of an intermetal dielectric (IMD). ITRS is an institutionwhich defines objectives for ensuring progress in integrated circuittechnology. According to the ITRS Roadmap, in 2008 the demand will befor a k value of an intermetal dielectric of 1.5.

As illustrated in FIG. 1A, for an effective k value k_(por), the hostmaterial, i.e. the homogenous, pore-free material, must have a k valuek_(hom) of approximately 2.1, working on the basis of the pores forming50% by volume. A material of this type is not currently known for use insilicon process technology.

In particular, the concept of gradually increasing the proportion of aporous dielectric which is formed by cavities is limited by the factthat if this proportion by volume becomes too high, the mechanicalstability of the dielectric layer deteriorates and the heat conductionproperties, which are of relevance to the dissipation of losses causedby resistance in interconnects, also deteriorate. Therefore, to achievea sufficiently low k value, the solution of increasing the proportion ofcavities to an ever greater extent is reaching its limits.

The dependent relationship between the effective k value k_(eff) and thepore cross-sectional area is shown in a semi-logarithmic illustrationfor different pore shapes and pore geometries in the diagram 110 shownin FIG. 1B.

The pore cross-sectional area is plotted in logarithmic form on anabscissa 111, and the effective k value k_(eff) is plotted on theordinate 112. A first curve 113, a second curve 114, a third curve 115and a fourth curve 116, which run through the corresponding data points,are plotted in the diagram 110. In all cases, the pores are assumed toform 50% by volume, and the host material is assumed to be silicondioxide with a (homogenous) k value of 4.0.

The second curve 114 corresponds to the case of pores with a circularcross section, the third curve 115 corresponds to pores with a squarecross-sectional area. The first curve 113 and the fourth curve 116 showthe dependent relationship for a pore with a rectangular cross-sectionalarea, which in the case of the first curve 113 is oriented parallel toan external electrical field and in the case of the fourth curve 116 isoriented perpendicular to an external electrical field.

The simulation calculations which are described and known fromSteinhögl, W, Schindler, G (2001) “Towards Minimum k Values of PorousDielectrics: A Simulation Study”, Advanced Metallization Conference,Oct. 9-11, 2001, Montreal demonstrate that the effective k valuedecreases to a greater extent with the pores oriented perpendicular toan electric field than in the case of a parallel orientation between thedirection in which the pores run and the electric field vector.

In other words, if elongate and oriented pores are used, it is possibleto significantly reduce the effective k value k_(eff) without increasingthe proportion of the volume which is made up of the pores. With thesame proportion of pores by volume, a reduction of 13% is achieved witha pore aspect ratio of 4:1, and a reduction of 20% is achieved with apore aspect ratio of 24:1. If the pores are randomly oriented, there isno advantage over round pores (aspect ratio 1:1). In this case, the samemean k value is obtained.

However, the formation of oriented pores in a dielectric withcross-sectional areas sufficiently small for preferably a multiplicityof such pores to be arranged between adjacent interconnects of anintegrated circuit, which are typically arranged at a distance F fromone another, imposes considerable technological demands. In thiscontext, F denotes the minimum feature sizes that can usually beachieved using a specific technology.

The following process for producing a porous dielectric is known fromthe prior art. Two liquid components, of which one is dielectric in thesolidified state and the other is, for example, a pore-forming agent,are mixed and brought to an elevated temperature at which only the firstcomponent solidifies, and in so doing encloses liquid pore-formingagent. If the inclusions of pore-forming agent are converted into thegas phase, what remains is a porous dielectric.

However, the process described cannot be used to produce oriented pores,which have particularly advantageous properties (cf. FIG. 1B), and theprocess is limited to dielectrics which are in a settable liquid phase.

U.S. Pat. No. 5,461,003 discloses a process for forming air gaps betweenthe metal lines of a semiconductor device.

EP 1 061 043 A1 describes a low-temperature process for synthesizingcarbon nanotubes using a metal catalyst layer for decomposing a carbonsource gas.

U.S. 2001/0024633 A1 discloses a process for the vertical alignment ofcarbon nanotubes on substrates at low pressure and low temperature usinga CVD process.

U.S. Pat. No. 6,277,318 B1 discloses a process for producing structuredcarbon nanotube films.

SUMMARY

The invention is based on the problem of introducing elongate, orientedpores into a dielectric in order thereby to reduce the effective k valueof a dielectric.

The problem is solved by a process for producing a layer arrangement andby a layer arrangement having the features described in the independentpatent claims.

In one embodiment, the invention provides a process for producing alayer arrangement, in which two electrically conductive interconnectsrunning substantially parallel to one another are formed on a substrate,at least one auxiliary structure is formed on the substrate and betweenthe two interconnects, running in a first direction, which firstdirection includes an acute or right angle of at least 45° with aconnecting axis of the interconnects, running orthogonally with respectto the two interconnects, the at least one auxiliary structure beingproduced from a material which allows the at least one auxiliarystructure to be selectively removed from the dielectric layer and inwhich process, a dielectric layer is formed between the twointerconnects, in such a manner that the at least one auxiliarystructure is at least partially covered by the dielectric layer.

Evidently, at least one auxiliary structure is formed at apredeterminable direction on the substrate and between interconnectsarranged on the substrate, and this at least one auxiliary structure isat least partially covered by a dielectric layer. Furthermore, theselectivity with which the auxiliary structures can be removed withrespect to the dielectric layer is utilized; this selectivity resultsfrom the material used for the auxiliary structure. In other words, theauxiliary structures (which are evidently sacrificial structures) can beremoved after application of the dielectric layer, so that orientedpores then remain in the dielectric layer at the locations at which theauxiliary structures were previously arranged. As has been describedabove with reference to FIG. 1B, by suitably selecting the orientation(corresponding to the angle between the connecting axis of theinterconnects and the direction in which the auxiliary structures run inaccordance with the invention), it is possible to reduce the effective kvalue of the dielectric layer and thereby to produce a “low-kdielectric”. Conversely, given a predetermined set value for therelative dielectric constant for a predetermined host material, it ispossible to reduce the proportion by volume of pores in the dielectriclayer, thereby ensuring sufficient dissipation of waste heat produced byresistance losses and a sufficient mechanical stability of the porousdielectric layer. The dissipation of heat from a tube structure of thistype is particularly expedient, since the heat conduction parallel tothe tubes is higher than perpendicular thereto. This allows the transferof heat toward the top surface and the back surface of the substrate tobe improved. The result is a very effective dissipation of the thermalpower loss produced in the interconnects. Furthermore, all the processsteps mentioned can be realized using tried-and-tested standardsemiconductor technology processes which are available in numeroussemiconductor technology laboratories and factories and can be carriedout at low cost. It is particularly advantageous that the auxiliary orsacrificial structures can be removed without destroying or damaging thedielectric.

The invention makes use of the physical discovery that elongate poreswith an orientation that is preferably perpendicular to the twointerconnects and therefore perpendicular to the electric field lines ofan electric field between the two parallel interconnects allow the kvalue to be reduced by 15% or more. Therefore, an oriented tubestructure of this type can be used as “low-k dielectric” in aninsulating material.

By way of example, with the process according to the invention it ispossible to produce a tubular structure by free-standing, orientedauxiliary structures, for example carbon nanotubes, being deposited onthe substrate, dielectric material being deposited conformally on theauxiliary structures and then the auxiliary structures being convertedinto the gas phase without the dielectric material being destroyed. Inthe case of carbon nanotubes, for example, it is possible to incinerateor burn the carbon nanotubes in an oxygen-containing atmosphere at asufficiently high temperature, so that they are oxidized to form carbondioxide.

Furthermore, the invention provides a layer arrangement, having asubstrate, two electrically conductive interconnects runningsubstantially parallel to one another on the substrate, a dielectriclayer between the two interconnects and at least one auxiliarystructure, which extends in a first direction starting from the surfaceof the substrate, at least partially in the dielectric layer and betweenthe two interconnects, which first direction includes an acute or rightangle of at least 45° (degrees) with a connecting axis of theinterconnects running orthogonally with respect to the twointerconnects, the at least one auxiliary structure being produced froma material which allows the at least one auxiliary structure to beselectively removed from the dielectric layer.

Preferred refinements of the invention will emerge from the dependentclaims.

In the process according to the invention, a layer of catalyst materialfor catalyzing the formation of the auxiliary structure can be formedbetween at least part of the substrate and the at least one auxiliarystructure.

By forming a layer of catalyst material, it is possible for theauxiliary structures to be applied in targeted positions and under moregentle conditions (e.g. at a lower temperature) than if a layer ofcatalyst material is not used. This simplifies and improves theproduction process.

Furthermore, an electrically insulating auxiliary layer, which may beproduced in particular from silicon dioxide or silicon nitride, may beformed between the layer of catalyst material and the substrate.

According to an advantageous refinement, at least one of the at leastone auxiliary structures can be selectively removed from the dielectriclayer.

As a result, oriented pores remain in the dielectric layer, therebyproducing the advantageous effects which have been described above.

In particular, according to the process of the invention, it is possiblefor at least one of the at least one auxiliary structures to be formedas a carbon nanotube, and for the at least one carbon nanotube to beselectively removed in a dielectric layer by increasing the temperaturein an oxygen atmosphere.

A carbon nanotube is particularly suitable for use as auxiliarystructure. By way of example, Harris, P J F (1999) “Carbon Nanotubes andRelated Structures—New Materials for the Twenty-first Century.”,Cambridge University Press, Cambridge. pp. 1 to 15, 111 to 155 providesan overview of carbon nanotubes. A nanotube is a single-walled ormulti-walled, tubular carbon compound. In the case of multi-wallednanotubes, at least one inner nanotube is coaxially surrounded by anouter nanotube. Single-walled nanotubes typically have diameters of 1nm, and the length of a nanotube may be several 100 nm. The ends of ananotube are often terminated with in each case half a fullerenemolecule. Processes for producing carbon nanotubes on a substrate aredescribed, for example, in Xu, X et al. (1999) “A method for fabricatinglarge-area, patterned, carbon nanotube field emitters” Applied PhysicsLetters 74(17):2549-2551, Ren, Z F et al. (1999) “Growth of a singlefreestanding multiwall carbon nanotube on each nanonickel dot” AppliedPhysics Letters 75(8):1086-1088. The CVD (chemical vapor deposition)process is often used for this purpose.

Carbon nanotubes can be formed on the surface of the substrate in themanner described and conformally covered with a dielectric layer. Use isthen made of the selectivity with which the carbon nanotubes and thedielectric can be removed. In an oxygen plasma, the carbon nanotubes areburnt to form carbon dioxide, whereas the dielectric layer is notremoved by an oxygen plasma. Therefore, what remains is a dielectriclayer with structured nanopores, which can be used as a low-k material.

According to another refinement of the process according to theinvention for producing a layer arrangement, the dielectric layer isformed before the interconnects, and the interconnects are formed usingthe Damascene process in the dielectric layer.

Alternatively, the dielectric layer may be formed after theinterconnects.

The layer arrangement produced in accordance with the invention isdescribed in more detail in the text which follows. Configurationsrelating to the layer arrangement also apply to the process forproducing a layer arrangement, and vice versa.

In the layer arrangement according to the invention, it is preferablefor the angle included between the first direction and the connectingaxis to be 90 degrees.

It is particularly expedient to produce tubular pores with anorientation perpendicular to the surface of the substrate, since thisparticularly greatly reduces the coupling capacitance between theinterconnects of a metallization level with a given proportion of thevolume formed by the pores.

It is preferable for the substrate to be a silicon substrate.

The dielectric layer may include silicon dioxide (SiO₂), silicon oxidewith fluorine, hydrogen, carbon and/or alkyl groups (in particular CHgroups), SiLK™, parylene, benzocyclobutene (BCB), polybenzoxazole (PBO),hydrogen silsesquioxane (HSQ) or methyl silsesquioxane (MSQ).

The at least one auxiliary structure may be a nanotube, a nanorod or apolymer.

However, it is also possible for any other suitable structure, forexample carbon fibers or other fibers of sufficiently small dimensionswhich can be applied in oriented fashion to a substrate, to be used asthe auxiliary structure.

If at least one of the at least one auxiliary structures is formed as ananorod, this nanorod may include silicon, germanium, indium phosphideand/or gallium arsenide. If at least one of the at least one auxiliarystructures is a nanotube, this may, for example, be a carbon nanotube, atungsten sulfide nanotube or another chalcogenide nanotube. In the caseof a carbon nanotube, this may be a pure carbon nanotube or a carbonnanotube with at least one further element, such as for example acarbon-nitrogen nanotube or a carbon-boron-nitrogen nanotube.

The nanostructures described are described, for example, in Roth, S(200)“Leuchtdioden aus Nanostäbchen”, [light-emitting diodes formed fromnanorods], Physikalische Blätter 57(5):17f. In addition to carbonnanotubes, by way of example nanotubes made from tungsten sulfide andother chalcogenides are also known. Furthermore, in addition to thehollow nanotubes, nanorods are also being investigated. Like nanotubes,nanorods have a diameter in the nanometer range, but may be up to a fewmicrometers long. In this case, they are molecule-like in cross sectionbut compatible with current semiconductor technology over their length.Typical materials used for nanorods are the semiconductors silicon,germanium, indium phosphide and gallium arsenide. Like the carbonnanotubes, the nanorods can also be deposited from the vapor phase usingcatalytic processes.

According to a refinement of the layer arrangement according to theinvention, a layer of catalyst material for catalyzing the formation ofthe auxiliary structure may be arranged between at least part of thesubstrate and the at least one auxiliary structure.

The layer of catalyst material may in particular have a plurality ofnoncohesive sections on the surface of the substrate. The auxiliarystructure then grows preferentially on such spots, whereas regions onthe surface of the substrate which do not have catalyst material remainfree of auxiliary structures.

If, in the layer arrangement, at least one of the at least one auxiliarystructures is a carbon nanotube, a layer which includes iron, cobaltand/or nickel is particularly advantageous for use as the layer ofcatalyst material.

In particular, it is known that spots of a layer of catalyst material ofthis type on the surface of a substrate form regions from which thegrowth of the carbon nanotubes in a growth direction orthogonal withrespect to the substrate proceeds particularly effectively.

It is preferable for at least one of the at least one auxiliarystructures to have a substantially circular or rectangular cross sectionin a plane that is orthogonal to the first direction.

The surface plane of the substrate may in particular run orthogonally orparallel to the first direction, i.e. the auxiliary structures may beoriented in the substrate surface or perpendicular with respect thereto.

An electrically insulating interlayer may be arranged between the layerof catalyst material and the substrate.

Furthermore, at least one of the interconnects may be at least partiallysurrounded by a barrier layer, in order to avoid diffusion.

It is possible that undesirable diffusion may take place between aninterconnect, which is often made from copper material, and an adjoininginsulation layer, which is often formed from silicon dioxide. This iondiffusion has undesirable effects and can be avoided by at leastpartially surrounding the interconnects with a barrier layer, which maybe produced in particular from tantalum and/or tantalum nitride.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the present invention and are incorporated in andconstitute a part of this specification. The drawings illustrate theembodiments of the present invention and together with the descriptionserve to explain the principles of the invention. Other embodiments ofthe present invention and many of the intended advantages of the presentinvention will be readily appreciated as they become better understoodby reference to the following detailed description. The elements of thedrawings are not necessarily to scale relative to each other. Likereference numerals designate corresponding similar parts.

FIG. 1A illustrates a diagram plotting the dependent relationshipbetween the k value in a porous material and the k value in theassociated homogenous material,

FIG. 1B illustrates a diagram plotting the dependent relationshipbetween the effective k value of a porous dielectric and the geometry ofthe pores and the cross-sectional area of the pores,

FIG. 2A illustrates a layer arrangement according to a first exemplaryembodiment of the invention in a first operating state,

FIG. 2B illustrates the layer arrangement according to the firstexemplary embodiment of the invention as shown in FIG. 2A in a secondoperating state,

FIGS. 3A to 3G illustrate layer sequences at different times during theprocess according to the invention for producing a layer arrangement inaccordance with a first exemplary embodiment of the invention,

FIGS. 4A to 4G illustrate layer sequences at different times during theprocess for producing a layer arrangement in accordance with a secondexemplary embodiment of the invention.

DETAILED DESCRIPTION

In the following Detailed Description, reference is made to theaccompanying drawings, which form a part hereof, and in which is shownby way of illustration specific embodiments in which the invention maybe practiced. In this regard, directional terminology, such as “top,”“bottom,” “front,” “back,” “leading,” “trailing,” etc., is used withreference to the orientation of the Figure(s) being described. Becausecomponents of embodiments of the present invention can be positioned ina number of different orientations, the directional terminology is usedfor purposes of illustration and is in no way limiting. It is to beunderstood that other embodiments may be utilized and structural orlogical changes may be made without departing from the scope of thepresent invention. The following detailed description, therefore, is notto be taken in a limiting sense, and the scope of the present inventionis defined by the appended claims.

The following text, referring to FIG. 2A, describes a layer arrangement200 in accordance with a first exemplary embodiment of the invention.

The layer arrangement 200 includes a silicon substrate 201, two copperinterconnects 202, 203 running parallel to one another on the siliconsubstrate 201, a silicon dioxide dielectric layer 204 between the twointerconnects 202, 203 and three carbon nanotubes 205 a, 205 b, 205 c,extending in a first direction 206 from the surface of the siliconsubstrate 201, at least partially in the silicon dioxide dielectriclayer 204 and between the two interconnects 202, 203, which firstdirection 206 includes an acute angle α>45° with a connecting axis 207of the interconnects 202, 203, which runs orthogonally with respect tothe two interconnects 202, 203, with the carbon nanotubes 205 a, 205 b,205 c, which include carbon material, being directed in such a mannerthat the three carbon nanotubes 205 a to 205 c can be removedselectively from the silicon dioxide dielectric layer 204.

FIG. 2B illustrates a layer arrangement 210 which has been modified withrespect to the layer arrangement 200 shown in FIG. 2A. Identicalcomponents in FIG. 2B are provided with the same reference numerals asin FIG. 2A.

As shown in FIG. 2B, the carbon nanotubes 205 a to 205 c have beenremoved from the layer arrangement 210, whereas the silicon dioxidedielectric layer 204 has not been removed from the layer arrangement210, so that what remains is a first tube 211 a, a second tube 211 b anda third tube 211 c. A porous dielectric which includes tubular cavitieswhich are oriented at an angle α>45° with respect to an electric fieldbetween the two interconnects 202, 203 (an electric field of this typeis not shown in FIG. 2B), has been formed from the tubes (or pores) 211a to 211 c and the silicon dioxide dielectric layer 204, so that thesilicon dioxide dielectric layer 204 with the tubes 211 a to 211 c has alower dielectric constant than in the operating state with carbonnanotubes 205 a to 205 c shown in FIG. 2A.

The following text, referring to FIG. 3A to FIG. 3G, describes a processfor producing a layer arrangement in accordance with a first exemplaryembodiment of the invention.

FIG. 3A illustrated a layer sequence 300 as obtained at a first timeduring the production process according to the invention. The layersequence 300 is obtained by an electrically insulating interlayer 302 ofsilicon nitride being applied to a silicon substrate 301, and bycatalyst material for catalyzing the formation of carbon nanotubes beingapplied to part of the electrically insulating layer 302. According tothe exemplary embodiment described, the layer of catalyst materialencompasses the catalyst material spots 303. The thickness of thecatalyst material spots 303 is approximately 1 to 5 nm, and thesecatalyst material spots are produced from iron, nickel and cobalt. In asubsequent process step, they serve as nuclei for the growth of carbonnanotubes. The electrically insulating interlayer 302 is anapproximately 5 nm thick silicon nitride layer.

The layer sequence 310 illustrated in FIG. 3B is obtained by five carbonnanotubes 311 being formed on the surface of the layer sequence 300,more specifically on the catalyst material spots 303, and on a surfaceregion of the layer sequence 300 between two interconnects which are tobe applied in a subsequent process step, which carbon nanotubes 311 runin a first direction 312, which first direction 312 forms a right anglewith a connecting axis 313 running orthogonally with respect to the twointerconnects which are subsequently to be formed. The carbon nanotubes311 are produced from carbon material, so that the carbon nanotubes 311can be removed selectively from a dielectric layer formed in asubsequent process step. According to the exemplary embodiment of theinvention described, the carbon nanotubes 311 are formed using a CVD(chemical vapor deposition) process, in which the layer sequence 300 isexposed to a hydrogen atmosphere at a temperature of between 400° C. and750° C. for approximately 5 minutes, and then acetylene is introduced inthe process chamber as a carbon source for approximately 2 to 10minutes. With this process, it is possible to produce carbon nanotubes311 which are approximately 10·m long and which, as shown in FIG. 3B,are arranged perpendicularly on the planar surface of the layer sequence310.

It should be noted that the invention is not restricted to the scenarioillustrated in FIG. 3B, in which in each case one carbon nanotube isgrown on each catalyst spot. If the process parameters (e.g., size ofthe catalyst material spots, etc.) are selected accordingly, it ispossible for a plurality of carbon nanotubes, for example a tuft ofcarbon nanotubes, to be grown on one catalyst material spot.

The layer sequence 320 illustrated in FIG. 3C is obtained by adielectric layer 321 being formed in a region between the twointerconnects which are to be formed in a subsequent process step, insuch a manner that the carbon nanotubes 311 are partially covered by thedielectric layer 321 of silicon dioxide material. The dielectric layer321 is formed using a CVD process. Alternatively, the material of thedielectric layer 321 may be silicon nitride or what is known as aspin-on glass. A spin-on glass is produced by spinning on liquidglasses, for example formed from dissolved siloxenes, spin-on glassbeing applied to a layer sequence by means of spin-on coating in asimilar manner to resist, flowing at room temperature and therebyfilling up trenches at the surface and leveling any steps.

The layer sequence 330 illustrated in FIG. 3D is obtained by the carbonnanotubes 311 being removed selectively from the dielectric layer 321.The carbon nanotubes 311 are removed selectively from the dielectriclayer 321 by increasing the temperature in an oxygen atmosphere. As aresult, what remains are tubular, oriented pores 331 in the layersequence 330. The carbon nanotubes 311 enclosed in the dielectric layer321 (optionally after the dielectric layer 321 has been etched back in ascenario which deviates from FIG. 3C and in which the carbon nanotubes311 are completely covered by the dielectric layer 321) are evidentlyincinerated by means of an oxygen plasma, so that what remains is adielectric layer 321 studded with the tube-like pores 331.

According to the exemplary embodiment of the process for producing alayer arrangement described, the dielectric layer 321 is formed beforethe interconnects, and the interconnects are formed using the Damasceneprocess in the dielectric layer 321, as described below.

In the Damascene technique for producing leveled interconnects, first ofall an intermetal dielectric is applied to a layer, trenches are etchedinto this intermetal dielectric and these trenches are filled withmetal. For this purpose, the metal is first of all deposited over theentire surface and then removed again, for example by CMP (chemicalmechanical polishing) or by etching back exposed regions.

To obtain the layer sequence 340 illustrated in FIG. 3E, trenches 341,342 are introduced into the surface of the layer sequence 330 in surfaceregions in which the interconnects are formed in a subsequent processstep. This is realized by means of a suitable lithography anddry-etching process.

The layer sequence 350 illustrated in FIG. 3F is obtained by the firsttrench 341 and the second trench 342 being lined with a barrier layer351 of tantalum nitride. The barrier layer 351 of tantalum nitrideprevents copper material from the interconnects that are subsequentlyformed from diffusing into the dielectric layer 321.

To obtain the layer arrangement 360 according to the inventionillustrated in FIG. 3G, the first and second trenches 341, 342, whichhave been lined with the barrier layer 351 of tantalum, are filled withcopper material. This forms the first and second interconnects 361, 362.This is realized by first of all applying a copper seed layer, i.e. athin film of copper, to the barrier layers 351 in the trenches 341, 342,which copper seed layer ensures that copper material which issubsequently applied is applied to the regions within the trench whichare defined by the copper seed layer. The filling of the trenches 341,342 lined with the barrier layer 351 and the copper seed layer (notillustrated in FIG. 3G) is carried out using an electroplating process.

The result is the layer arrangement 360 illustrated in FIG. 3G. In thislayer arrangement, the first direction 312 is oriented orthogonally withrespect to the connecting axis 313 of the first and second interconnects361, 362 and therefore orthogonally with respect to an electric fieldgenerated by electric charge carriers on the interconnects 361, 362,resulting in a material with a particularly low dielectric constant (cf.FIG. 1B).

The text which follows, referring to FIG. 4A to FIG. 4G, describes aprocess for producing a layer arrangement in accordance with a secondpreferred exemplary embodiment of the invention.

According to this exemplary embodiment of the production processaccording to the invention, the dielectric layer is formed after theinterconnects.

To obtain the layer sequence 400 shown in FIG. 4A, two electricallyconductive interconnects 402, 403 running parallel to one another areformed on a silicon substrate 401. Furthermore, FIG. 4A illustrates aphotoresist part-layer 404 on the interconnects 402, 403, originatingfrom a patterning process used to form the interconnects 402, 403 froman electrically conductive layer.

The layer sequence 410 illustrated in FIG. 4B is obtained by catalystmaterial spots 411 for catalyzing the formation of an auxiliarystructure in a subsequent process step being formed on part of thesilicon substrate 401. As illustrated in FIG. 4B, some of the catalystmaterial spots 411 are formed on the photoresist part-layer 404.

The layer sequence 420 illustrated in FIG. 4C is obtained by removingthe photoresist part-layer 404 from the interconnects 402, 403 using alift-off process. As a result, those catalyst material spots 411 whichwere applied to the photoresist part-layers 404 are removed from thelayer sequence 410.

To obtain the layer sequence 430 illustrated in FIG. 4D, three carbonnanotubes 431 are formed on the silicon substrate 401 and between thetwo interconnects 402, 403, running in a vertical direction 432 as shownin FIG. 4D, which vertical direction 432 substantially includes a rightangle with a connecting axis 433 running orthogonally with respect tothe two interconnects 402, 403, the carbon nanotubes 431 includingcarbon material, so that the carbon nanotubes 431 can be removedselectively from a dielectric layer that is to be applied in a furtherprocess step. The connecting axis 433 runs in the horizontal directionin accordance with FIG. 4D.

To obtain the layer sequence 440 illustrated in FIG. 4E, a dielectricsilicon dioxide layer 441 is formed between the two interconnects 402,403, in such a manner that the carbon nanotubes 431 are partiallycovered by the dielectric silicon dioxide layer 441. This is realizedusing a CVD process.

To obtain the layer sequence 450 illustrated in FIG. 4F, the carbonnanotubes 431 are removed selectively from the dielectric silicondioxide layer 441 by the carbon nanotubes 431 being removed selectivelyfrom the dielectric silicon dioxide layer 441 as a result of thetemperature being increased in an oxygen atmosphere. The material of thecarbon nanotubes 431 is incinerated as a result, so that trenches (orpores) 451 remain in the dielectric silicon dioxide layer 441.

To obtain the layer arrangement 460 illustrated in FIG. 4G, the layersequence 450 is treated with a CMP process in order to obtain a planarsurface.

1. A process for producing a circuit arrangement having a layerarrangement, in which two electrically conductive interconnects runningsubstantially parallel to one another are formed on a substrate,comprising; forming at least one auxiliary structure on the substrateand between the two interconnects, running in a first direction, whichfirst direction includes an angle of between 45 degrees and 90 degreeswith a connecting axis of the interconnects, running orthogonally withrespect to the two interconnects, the at least one auxiliary structurebeing produced from a material which allows the at least one auxiliarystructure to be selectively removed from a dielectric layer; forming thedielectric layer between the two interconnects, in such a manner thatthe at least one auxiliary structure is at least partially covered bythe dielectric layer; and forming a layer of catalyst material forcatalyzing the formation of the auxiliary structure between at leastpart of the substrate and the at least one auxiliary structure.
 2. Theprocess of claim 1, comprising forming an electrically insulatinginterlayer between the layer of catalyst material and the substrate. 3.The process of claim 1, comprising selectively removing at least one ofthe at least one auxiliary structures from the dielectric layer.
 4. Aprocess for producing a circuit arrangement having a layer arrangement,in which two electrically conductive interconnects running substantiallyparallel to one another are formed on a substrate, comprising: formingat least one auxiliary structure on the substrate and between the twointerconnects, running in a first direction, which first directionincludes an angle of between 45 degrees and 90 degrees with a connectingaxis of the interconnects, running orthogonally with respect to the twointerconnects, the at least one auxiliary structure being produced froma material which allows the at least one auxiliary structure to beselectively removed from a dielectric layer; forming the dielectriclayer between the two interconnects, in such a manner that the at leastone auxiliary structure is at least partially covered by the dielectriclayer; selectively removing at least one of the at least one auxiliarystructures from the dielectric layer; forming at least one of the atleast one auxiliary structures as a carbon nanotube; and selectivelyremoving the at least one carbon nanotube from the dielectric layer byincreasing the temperature in an oxygen atmosphere.
 5. The process ofclaim 1, comprising: forming the dielectric layer before theinterconnects; and forming the interconnects using the Damascene processin the dielectric layer.
 6. The process of claim 1, comprising formingthe dielectric layer after the interconnects.
 7. An arrangement having adielectric layer and electrically conductive interconnects comprising: asubstrate; two electrically conductive interconnects runningsubstantially parallel to one another on the substrate; a dielectriclayer between the two electrically conductive interconnects, thedielectric layer comprising elongated nanopores; and free-standingoriented sacrificial structures in the elongated nanopores, wherein thefree-standing oriented sacrificial structures extend along alongitudinal axis from the surface of the substrate, at least partiallyin the elongated nanopores of the dielectric layer and between the twointerconnects, the longitudinal axis including an angle of between 45degrees and 90 degrees with a connecting axis of the interconnectsrunning orthogonally with respect to the two interconnects.
 8. Thearrangement of claim 7, in which the angle included between thelongitudinal axis and the connecting axis is 90 degrees.
 9. Thearrangement of claim 7, in which the substrate is a silicon substrate.10. The arrangement of claim 7, in which the dielectric layer isselected from a group comprising: silicon dioxide; silicon oxide withfluorine, hydrogen, carbon and/or alkyl groups; Parylene;Benzocyclobutene; Polybenzoxazole; hydrogen silsesquioxane; or methylsilsesquioxane.
 11. The arrangement of claim 7, in which a layer ofcatalyst material for catalyzing the formation of the sacrificialstructures is arranged between at least part of the substrate and thesacrificial structure.
 12. The arrangement of claim 11, in which atleast one of the elongate nanopores comprises: a nanotube; a nanorod; ora polymer.
 13. The arrangement of claim 12, in which the nanorodcomprises: Silicon; Germanium; indium phosphide; and/or galliumarsenide.
 14. The arrangement of claim 12, in which the nanotubecomprises: a carbon nanotube; a tungsten sulfide nanotube; or achalcogenide nanotube.
 15. The arrangement of claim 12, in which thesacrificial structures are carbon nanotubes, and in which the layer ofcatalyst material comprises iron, cobalt, and/or nickel.
 16. The layerarrangement of claim 7, in which in which the sacrificial structures, ina plane orthogonal to the longitudinal axis, comprises a substantiallycircular or rectangular cross section.
 17. The arrangement of claim 7,comprising in which a surface plane of the substrate runs orthogonallyor parallel to the longitudinal axis.
 18. The arrangement of claim 17,comprising in which an electrically insulating interlayer is arrangedbetween the layer of catalyst material and the substrate.
 19. Thearrangement of claim 7, comprising in which at least one of theinterconnects is at least partially surrounded by a barrier layer, inorder to avoid diffusion.
 20. The arrangement of claim 19, in which thebarrier layer comprises tantalum, and/or tantalum nitride.
 21. A processfor producing a semiconductor arrangement, having a dielectric layer andelectrically conductive interconnects, the process comprising: formingtwo electrically conductive interconnects running substantially parallelto one another on a substrate; forming free-standing, orientedsacrificial structures on the substrate and between the twointerconnects, a longitudinal axis of the sacrificial structuresincluding an angle of between 45 degrees and 90 degrees with aconnecting axis of the interconnects running orthogonally with respectto the two interconnects, the sacrificial structures being produced froma material which is such that the sacrificial structures can beselectively removed from the dielectric layer; forming the dielectriclayer after the sacrificial structures have been formed, between the twointerconnects, in such a manner that the sacrificial structures are atleast partially enclosed by the dielectric layer; and selectivelyremoving the sacrificial structures from the dielectric layer.